This application claims priority under 35 USC § 119 to Korean Patent Application No. 2006-105039, filed on Oct. 27, 2006 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to on die termination in semiconductor memory devices, and more particularly, to determining on die termination modes in a semiconductor memory device.
2. Background of the Invention
On die termination (ODT) is used for improving signal integrity (SI) by minimizing signal reflection at an interface between a system and a memory device. In particular, signal reflection more significantly degrades SI in a memory system having high-speed operations. For suppressing signal reflection, a transmission line for signal transmission between the system and the memory device is terminated at a termination register (RTT).
Conventionally, input/output terminals of a memory controller or the memory device in the memory system include the ODT terminated at the RTT. The RTT is set to match an impedance of the transmission line.
The following is a brief description regarding the termination of the transmission line at the RTT. Assuming that there is a memory module with two memory ranks, when data is read from a memory in a first rank by the memory controller, an activated ODT signal is applied to a memory in a second rank by the memory controller. Then, the memory in the second rank forms a termination on a data bus shared with the first rank. This is called “termination register (RTT) formation”.
A specific example of a memory module comprising an ODT circuit is provided in U.S. Pat. No. 6,847,225, to Viehmann et al. issued on Jan. 25, 2005.
FIG. 1 is a timing diagram illustrating a normal ODT mode and a dynamic ODT mode. As described above, ODT is conventionally used to enhance the SI. Furthermore, in order to enhance SI when writing, the dynamic ODT mode is applied to Double Data rate, third generation memory chips (DDR3). Since an RTT for optimizing the SI in normal operation is different from that in the writing operation, the dynamic ODT mode is used for the writing operation. In other words, a DDR3 memory chip operates in the normal ODT mode and the dynamic ODT mode.
When the ODT signal is activated to a logic high state, the normal ODT mode is enabled so that the data bus is terminated at a normal termination register RTT_N. In the prior art, if a write command signal WC is activated while the ODT signal is activated so that the normal ODT mode is enabled, the dynamic ODT mode is enabled so that the data bus is terminated at a dynamic termination register RTT_D. In other words, only when the write command signal WC is activated in a state where the ODT signal is activated so that the normal ODT mode is enabled, the dynamic ODT mode is subsequently enabled.
Verification of enablement of the normal ODT mode is possible in the prior art. However, verification of enablement of the dynamic ODT mode is difficult in the prior art because the dynamic ODT mode is enabled while the normal ODT mode is also enabled.